(1) Field of the Invention
The present invention relates generally to a novel test structure and process for automatic Dynamic Negative-Bias Temperature Instability (DNBTI) testing of semiconductor devices to improve device reliability and performance.
(2) Description of Prior Art
As feature sizes for semiconductor devices decrease, along with the decrease in thickness of gate oxide layers, Negative Bias Temperature Instability (NBTI) has become an increasing reliability and performance concern. NBTI is not limited exclusively to short channel devices, but is directly related to device size reduction in the vertical direction. The theory of the NBTI degradation mechanism is complex, but is generally believed to be caused by the generation of interface traps in the device silicon generated by negative bias and accelerated by high temperature. These interface traps cause degeneration of device threshold characteristics, particularly for PMOS devices. It is therefore most important to test and model the lifetime of PMOS devices used in integrated circuits to assure proper circuit operation over device lifetime.
The conventional prior art method of determining device margin, and hence lifetime, for PMOS devices has been a constant voltage DC gate stress, often combined with high ambient stress test temperature.
High ambient stress was deemed important because it has been found that for devices that are subject to high-temperature conditions, whether due to the chips own heat dissipation or the environment in which the chip is used, NBTI failures will occur which would not be projected by the prior art burn-in testing alone, or prior art DC stress testing alone.
A conventional DC gate stress test configuration is illustrated in FIG. 1. As shown in the figure, a constant negative DC bias is applied to the gate electrode 16 of a PMOS transistor 12. The Source/Drain (S/D) 14 of the transistor as well as the channel substrate or N-well 10 is grounded. The test is most commonly performed at high temperature, typically 100 degrees Centigrade (° C.). Periodic measurements are made of device characteristics, and by modeling lifetime projections are made.
However, the PMOS device is most typically used in a complimentary PMOS-NMOS or inverter configuration 22 shown in Prior Art FIG. 2(A). This circuit configuration is typically used in dynamic applications, not static or DC. The amount of device degradation due to Negative-Bias Temperature Instability (NBTI) is not constant for each device, but is a function of the devices unique switching activity within each circuit, that is, the device dynamic situation.
This is discussed in the paper “Dynamic NBTI of P-MOS Transistors and its Impact on MOSFET Scaling” by G. Chen, M. F. Li, C. H. Ang, J. Z. Zehng, and D. L. Kwong, IEEE Electron Device Letters, vol. 23, pp. 74-736, December 2002. The paper shows a nominal 10 times lifetime scaling for a dynamic projection over a static one.
This is illustrated in the referenced papers FIG. 4 and reproduced here as prior art FIG. 2(B) for convenience. The improvement in lifetime projection is attributed to what the reference paper calls, “electric passivation” (EP). This “EP” occurs during the “off” or “low output” cycle of the inverter, when a positive voltage is present at the PMOS gate.
Prior art FIG. 2(A), shows that during the dynamic operation of a P-MOS FET (22) in a CMOS inverter (20) the applied gate test bias (Vg/Vin) is switched between “high” and “low” voltages, while the drain bias (Vd/Vout) is correspondingly alternating between “low” and “high” voltages. This is the dynamic test condition for Dynamic Negative-Bias Temperature Instability (DNBTI).
As mentioned, FIG. 2(B) compares the lifetime projection for both Static NBTI (SNBTI) as tested in FIG. 1, and Dynamic (DNBTI) as tested in FIG. 2(A). As shown in FIG. 2(B), under the same stress voltage, the lifetime predicted by DNBTI is approximately a magnitude longer than predicted by SNBTI. Therefore, it is critically important for integrated circuits to investigate NBTI under such dynamic-stress conditions.
FIG. 3A outlines an actual test setup for DNBTI as illustrated on a cross section representation of a PMOS device. To simulate the DNBTI condition, a train of square waves Vg switching between “high” and “low” voltages is applied to the gate 30G, while the drain bias Vd is correspondingly alternating between “low” and “high” voltages, or 180 degrees phase shift from the gate voltage Vg.
Representative opposite phase square wave trains are illustrated in Prior Art FIG. 3(B). A negative Vg turns the device 30 “on” causing the voltage at the drain 30D to go low. This drain voltage therefore is a 180-degree phase shift from the input or gate voltage.
The test setup is illustrated in Prior Art FIG. 3(C). A phase 1 pulse generator Vg is attached through switch SW 1 to the gate 30G of the PMOS device under test (DUT) 30. On the open pole SW 1-2 of switch SW 1 is-a block designated “DC SMU-G” 44 (DC Source Measurement Unit-Gate). This represents the instrumentation required to periodically monitor the DUT 30 operational characteristics, particularly threshold voltage.
The DUT 30 drain 30D is connected to the common pole of switch 2 SW2 that in turn is connected through the closed pole SW2-1 of switch SW2 to a second pulse generator Vd that is 180 degrees out of phase with the phase 1 pulse generator Vg. In order to simulate the DNBTI condition, a train of square waves Vg is applied to the gate 30G though switch SW1, and an opposite phase signal Vd is applied to the drain through switch SW2. Switching SW1 and SW2 to the DC Source Measurement Units 44, 46, will enable device characterization measurements. Upon completing the device measurements the switches are returned to the stress positions and the stress testing can continue.
It is a tedious job to make the phase relationship of the two pulses exactly opposite, or 180 degrees out of phase. Proper test voltage phase relationship is important to achieve meaningful test results. An external inverter could possibly alleviate the phase relationship adjustment; but external LC coupling can limit high frequency testing.
To summarize the external test setup requirements, two external pulse outputs are required along with two switches and several SMU units. Overall, the test setup can be tedious and time consuming, and could lead to misleading results if not done properly.
The following patents describe semiconductor and NBTI testing and modeling.
U.S. Pat. No. 6,653,856 (Liu) shows NBTI testing according to the prior art of the present invention.
U.S. Pat. No. 6,476,632 (LaRosa et al.) shows a ring oscillator design for MOSFET device reliability testing including NBTI testing.
U.S. Pat. No. 6,649,984 (Noda et al.) teaches bum-in testing using an inverter.
U.S. Pat. No. 6,521,469 (LaRosa et al.) discusses in-line testing for NBTI using hole injection.
U.S. Pat. No. 6,456,104 (Guarin et al.) discloses a test structure to externally apply a stress voltage to the gate.
U.S. Pat. No. 6,671,844 (Krech, Jr. et al.) shows a memory tester with multiple DUT testing.
US Patent Application 2003/0233624 (Reddy et al.) discloses testing discrete transistors for NBTI to estimate degradation of an Integrated circuit.
In addition to the above patents, the following technical reports discuss NBTI. “Dynamic NBTI of P-MOS Transistors and its Impact on MOSFET Scaling” by G. Chen, M. F. Li, C. H. Ang, J. Z. Zehng, and D. L. Kwong, IEEE Electron Device Letters, vol. 23, pp. 734-736, December 2002.
“Dynamic NBTI of P-MOS Transistors and its Impact on Device Lifetime” by G. Chen, K. Y. Chuah, M. F. Li, S. H. Chan, C. H. Ang, J. Z. Zheng, Y. Jin and D. L. Kwong,
International Reliability Physics Symposium Proceeding, Dallas Tex. USA, pp. 196-202, April 2003.